IDT7008L(2018) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT7008L
(Rev.:2018)

HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing(1,5)

tWC

ADDR"A"

CE"A"

INTERRUPT SET ADDRESS (2)

tAS(3)

tWR (4)

R/W"A"

INT"B"

ADDR"B"

CE"B"

tINS (3)

tRC

INTERRUPT CLEAR ADDRESS (2)

tAS(3)

3198 drw 17

OE"B"

INT"B"

tINR (3)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. See Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

5. Refer to Chip Enable Truth Table.

3198 drw 18

Truth Table IV — Interrupt Flag(1,4,5)

Left Port

R/WL

CE

OEL

A15L-A0L

INTL

R/WR

CE

L

L

X

FFFF

X

X

X

X

X

X

X

X

X

L

X

X

X

X

L(3)

L

L

X

L

L

FFFE

H(2)

X

X

NOTES:

1. Assumes BUSYL = BUSYR =VIH.

2. If BUSYL = VIL, then no change.

3. If BUSYR = VIL, then no change.

4. INTL and INTR must be initialized at power-up.

5. Refer to Chip Enable Truth Table.

Right Port

OER

A15R-A0R

X

X

L

FFFF

X

FFFE

X

X

INTR

Function

L(2) Set Right INTR Flag

H(3) Reset Right INTR Flag

X

Set Left INTL Flag

X

Reset Left INTL Flag

3198 tbl 16

61.452

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