IDT7008L(2018) 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT7008L Datasheet PDF : 20 Pages
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IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
7008X15
7008X20
7008X25
Com'l Only Com'l & Ind Com'l Only
7008X35
Com'l Only
7008X55
Com'l & Ind
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
____
15
____
20
____
20
____
20
____
45
ns
tBDA
BUSY Disable Time from Address Not Matched
____
15
____
20
____
20
____
20
____
40
ns
tBAC
BUSY Access Time from Chip Enable Low
____
15
____
20
____
20
____
20
____
40
ns
tBDC
BUSY Access Time from Chip Enable High
____
15
____
17
____
17
____
20
____
35
ns
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
15
____
20
____
25
____
35
____
55
ns
tWH
Write Hold After BUSY(5)
12
____
15
____
17
____
25
____
25
____
ns
BUSY TIMING (M/S=VIL)
tWB
BUSY Input to Write(4)
0
____
0
____
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
12
____
15
____
17
____
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
____
30
____
45
____
50
____
60
____
80
ns
____
25
____
30
____
35
____
45
____
65
ns
NOTES:
3198 tbl 14
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
12
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