IDT7006S(2018) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT7006S
(Rev.:2018)

HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7006S/L

High-Speed 16K x 8 Dual-Port Static RAM

Waveform of Read Cycles(5)

tRC

ADDR

CE

tAA(4)

tACE(4)

tAOE(4)

OE

Military, Industrial and Commercial Temperature Ranges

R/W

DATAOUT

tLZ(1)

VALID DATA(4)

tOH

tHZ(2)

BUSYOUT

tBDD(3,4)

2739 drw 07

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

CE

tPU

ICC

ISB

tPD

,

2739 drw 08

8

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