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IDT7006S(2018) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT7006S
(Rev.:2018)
IDT
Integrated Device Technology IDT
IDT7006S Datasheet PDF : 21 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Description
The IDT7006 is a high-speed 16K x 8 Dual-Port Static RAM. The
IDT7006 is designed to be used as a stand-alone 128K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
Military, Industrial and Commercial Temperature Ranges
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power. Low-power (L)
versions offer battery backup data retention capability with typical power
consumption of 500µW from a 2V battery.
The IDT7006 is packaged in a ceramic 68-pin PGA, an 68-pin quad
flatpack, a PLCC, and a 64-pin thin quad flatpack, TQFP. Military grade
product is manufactured in compliance with the latest revision of MIL-PRF-
38535 QML, Class B, making it ideally suited to military temperature
applications demanding the highest level of performance and reliability.
Pin Configurations(1,2,3)
INDEX
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
IDT7006J or F
55
16
J68(4)
54
17
F68(4)
53
18
52
68 Pin PLCC / Flatpack
19
Top View(5)
20
51
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
11/06/01
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
.
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
2739 drw 02a
INDEX
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in. x .17 in.
F68-1 package body is approximately .97 in x .97 in x .08 in.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking
I/O2L
1
I/O3L
2
I/O4L
3
I/O5L
4
GND
5
I/O6L
6
I/O7L
7
VCC
8
GND
9
I/O0R
10
I/O1R
11
I/O2R
12
VCC
13
I/O3R
14
I/O4R
15
I/O5R
16
2
7006PF
PN64(4)
64 Pin TQFP
Top View(5)
11/06/01
48
A4L
47
A3L
46
A2L
45
A1L
44
A0L
43
INTL
42
BUSYL
41 GND
40
M/S
39
BUSYR
38
INTR .
37
A0R
36
A1R
35
A2R
34
A3R
33
A4R
2739 drw 03a

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