IDT74FCT646 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT74FCT646 Datasheet PDF : 8 Pages
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IDT54/74FCT646/A/C
FAST CMOS OCTAL TRANSCEIVER/REGISTER
PIN CONFIGURATIONS
CPAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
24
2
23
3
22
4 P24-1, 21
5 D24-1, 20
6
S024-2
&
19
7 E24-1 18
8
17
9
16
10
15
11
14
12
13
Vcc
CPBA
SBA
G
B1
B2
B3
B4
B5
B6
B7
B8
DIP/SOIC/CERPACK
TOP VIEW
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX
4 3 2 28 27 26
A1 5
A2 6
1
25 G
24 B1
A3 7
23 B2
NC 8
L28-1
22 NC
A4 9
21 B3
A5 10
20 B4
A6 11
19 B5
12 13 14 15 16 17 18
LCC
TOP VIEW
2536 drw 02
PIN DESCRIPTION
Pin Names
Description
A1–A8
Data Register A Inputs
Data Register B Outputs
B1–B8
Data Register B Inputs
Data Register A Outputs
CPAB, CPBA
Clock Pulse Inputs
SAB, SBA
DIR, G
Output Data Source Select Inputs
Output Enable Inputs
2536 tbl 01
LOGIC SYMBOL
CPAB
SAB
DIR
CPBA
SBA
G
A1 A2 A3 A4 A5 A6 A7 A8
B1 B2 B3 B4 B5 B6 B7 B8
2536 drw 06
FUNCTION TABLE(2)
Inputs
G
DIR
CPAB
CPBA SAB
SBA
Data I/O(1)
A1–A8
B1–B8
Operation or Function
IDT54/74FCT646
H
X
H
X
H or L
H or L
X
↑
↑
X
X
Input
Input
Isolation
X
Store A and B Data
L
L
L
L
X
X
X
L
Output
Input
Real-Time B Data to A Bus
X
H or L
X
H
Stored B Data to A Bus
L
H
X
X
L
X
Input
Output
Real-Time A Data to B Bus
L
H
H or L
X
H
X
Stored A Data to B Bus
NOTES:
2536 tbl 02
G 1. The data output functions may be enabled or disabled by various signals at the or DIR inputs. Data input functions are always enabled, i.e., data at
the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
2. H = HIGH, L = LOW, X = Don’t Care, ↑ = LOW-to-HIGH Transition.
7.18
2
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