ICSSSTUA32S869B 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICSSSTUA32S869B

14-Bit Configurable Registered Buffer for DDR2

Integrated Circuit Systems 

ICSSSTUA32S869B

Advance Information

DUT

OUT

CL=5pF

See Note (1)

Testpoint

RL=1K

(1) CL includes probe and jig capacitance.

Figure 22 — Partial parity out load circuit

CK

VICR

CK

tPLH

VICR

tPHL

Vi(P-P)

VTT

VTT

Output

VTT = VDD/2

VICR Cross Point Voltage

Vi(P-P) = 600mV

tPLH and tPHL are the same as tPD.

Figure 23 — Partial parity out voltage waveform, propagation delay time with respect to CLK input

1173—10/28/05

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