ICSSSTUA32S869B 데이터 시트보기 (PDF) - Integrated Circuit Systems
부품명
상세내역
일치하는 목록
ICSSSTUA32S869B Datasheet PDF : 18 Pages
| |||
ICSSSTUA32S869B
Advance Information
Electrical Characteristics - DC
TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL PARAMETERS
CONDITIONS
VDDQ
VIK
II = -18mA
VOH
IOH = -100µA
IOH = 6mA
1.7V
1.7V
VOL
IOL = 100µA
IOL = 6mA
1.7V
1.7V
II All Inputs
VI = VDD or GND
1.9V
Standby (Static)
RESET# = GND
IDD
Operating (Static)
VI = VIH(AC) or VIL(AC),
RESET# = VDD
1.9V
RESET# = VDD,
Dynamic operating VI = VIH(AC) or VIL(AC),
(clock only)
CLK and CLK# switching
50% duty cycle.
RESET# = VDD,
IO = 0
IDDD
VI = VIH(AC) or VIL (AC),
Dynamic Operating CLK and CLK# switching
(per each data input) 50% duty cycle. One data
input switching at half
1.8V
clock frequency, 50%
duty cycle
Input capacitance,
Dn, PAR_IN inputs VI = VREF ± 250 mV
Input capacitance,
DCS#n
VI = VREF ± 250 mV
Input capacitance,
Ci
CK and CK# inputs2 VICR = 0.9V; VI(PP) = 600 mV
1.8V
Input capacitance,
RESET# input
VI = VDD or GND
Data Inputs
CLK and CLK#
RESET#
VI = VREF ±350mV
VICR = 1.25V, VI(PP) = 360mV
VI = VDDQ or GND
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - The vendor must supply this value for full device description.
MIN TYP
VDDQ - 0.2
1.2
MAX
-1.2
0.2
0.5
±5
0.2
TBD
UNITS
V
µA
µA
mA
TBD
µ/clock
MHz
TBD
µA/ clock
MHz/data
2.5
3.5
pF
2
3
pF
2
3
pF
Note 2
Note 2
pF
2.5
3.5
pF
2
3
2.5
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
PARAMETER
VDD = 1.8V ± 0.1V
MIN
MAX
UNIT
dV/dt_r
1
4
V/ns
dV/dt_f
1
4
dV/dt_∆1
1
V/ns
V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
1173—10/28/05
11
Share Link: 