ICS9148-11 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS9148-11

Frequency Generator & Integrated Buffers for PENTIUM™

Integrated Circuit Systems 

ICS9148 - 11

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized

inside the ICS9148.

3. All other clocks continue to run undisturbed.

4. PD# and CPU_STOP# are shown in a high (true) state.

PD# Timing Diagram

The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous

active low input.This signal is synchronized internal by theICS9148-11 prior to its control action of powering down the clock synthesizer.

Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state

and held prior to turning off theVCOs and the Crystal oscillator. The power on latency is guaranteed to be less than3mS.The power down

latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are don’t care signals during the power down operations.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device).

2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148.

3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.

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