ICS9148-11 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS9148-11 Datasheet PDF : 14 Pages
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Integrated
Circuit
Systems, Inc.
ICS9148 - 11
Frequency Generator & Integrated Buffers for PENTIUMTM
General Description
TheICS9148-11 generates all clocks required for high speed RISC
or CISC microprocessor systems such as Intel PentiumPro. An
output enable pin is provided for testability. MODE allows power
management functions: CPU_STOP#, PCI_STOP# &
PWR_DWN#.
High drive BCLK outputs typically provide greater than 1V/ns slew
rate into 30 pF loads. PCLK outputs typically provide better than 1V/
ns slew rate into 20 pF loads while maintaining50±5% duty cycle.
The REF clock outputs typically provide better than 0.5V/ns slew
rates.
Features
Generates four processor, six bus, one 14.31818MHz and 12
SDRAM clocks.
Synchronous clocks skew matched to 250ps window on
CPU, SDRAM and 500ps window on BUS clocks.
CPUCLKs to BUS clocks skew 1-4 ns (CPU early)
Test clock mode eases system design
Custom configurations available
VDD(1:3) - 3.3V ±10%
(inputs 5V tolerant w/series R )
VDDL(1:2) - 2.5V or 3.3V ±5%
PC serial configuration interface
Power Management Control Input pins
48-pin SSOP package
Block Diagram
Pin Configuration
9148-11 RevB 12/09/97P
48-Pin SSOP
Functionality
CPUCLK,
OE
SDRAM
(MHz)
0
High-Z
1
66.6
X1, REF
(MHz)
High-Z
14.318
PCICLK
(MHz)
High-Z
33.3
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
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