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ICS85408

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS85408

LOW SKEW, 1-TO-8

DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF in

single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

VDD

Single Ended Clock Input

V_REF

C1

0.1u

R1

1K

CLK

nCLK

R2

1K

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

LVDS DRIVER TERMINATION

A general LVDS interface is shown in Figure 2. In a 100Ω differ-

ential transmission line environment, LVDS drivers require a

matched load termination of 100Ω across near the receiver in-

put. For a multiple LVDS outputs buffer, if only partial outputs

are used, it is recommended to terminate the un-used outputs.

3.3V

Zo = 50 Ohm

3.3V

LVDS_DRIVER

R1

100

Zo = 50 Ohm

CLK

nCLK

HiPerClockS

85408BG

FIGURE 2. TYPICAL LVDS DRIVER TERMINATION

www.icst.com/products/hiperclocks.html

7

REV. A APRIL 25, 2005

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