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ICS8308AGI

LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS8308I

LOW SKEW, 1-TO-8

DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER

TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40° TO 85°

Symbol Parameter

Test Conditions

Minimum Typical Maximum

fMAX

Output Frequency

350

t

Propagation

Delay;

CLK, nCLK;

NOTE 1

IJ 350MHz

2

4

PD

LVCMOS_CLK;

NOTE 2

IJ 350MHz

2

4

tsk(o) Output Skew; NOTE 3, 7

Measured on

rising edge @VDDO/2

100

tsk(pp) Part-to-Part Skew; NOTE 4, 7

Measured on

rising edge @VDDO/2

1

tR / tF

Output Rise/Fall Time

0.6V to 1.8V

0.2

1.0

odc

Output Duty Cycle

IJ 150MHz, Ref = CLK, nCLK

45

55

tPZL, tPZH Output Enable Time; NOTE 5

5

tPLZ, tPHZ

tS

Output Disable Time; NOTE 5

Clock Enable

Setup Time;

NOTE 6

CLK_EN to

CLK, nCLK

CLK_EN to

LVCMOS_CLK

5

1

0

tH

Clock Enable

Hold Time;

NOTE 6

CLK, nCLK to

CLK_EN

LVCMOS_CLK

to CLK_EN

0

1

NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.

NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at VDDO/2.

NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with

equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.

NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.

NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.

Units

MHz

ns

ns

ps

ns

ns

%

ns

ns

ns

ns

ns

ns

8308AGI

www.icst.com/products/hiperclocks.html

6

REV. B JULY 25, 2005

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