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ICS8308AGI

LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS8308I

LOW SKEW, 1-TO-8

DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF in

single ended levels. The reference voltage V_REF = V /2 is

DD

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

VDD

Single Ended Clock Input

V_REF

C1

0.1u

R1

1K

CLK

nCLK

R2

1K

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

INPUTS:

OUTPUTS:

CLK INPUT:

For applications not requiring the use of the test clock, it can

be left floating. Though not required, but for additional

protection, a 1kΩ resistor can be tied from the CLK input to

ground.

LVCMOS OUTPUT:

All unused LVCMOS output can be left floating. We

recommend that there is no trace attached.

CLK/nCLK INPUT:

For applications not requiring the use of the differential input,

both CLK and nCLK can be left floating. Though not required,

but for additional protection, a 1kΩ resistor can be tied from

CLK to ground.

SELECT PINS:

All select pins have internal pull-ups and pull-downs;

additional resistance is not required but can be added for

additional protection. A 1kΩ resistor can be used.

8308AGI

www.icst.com/products/hiperclocks.html

10

REV. B JULY 25, 2005

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