HSP48410 데이터 시트보기 (PDF) - Intersil
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HSP48410 Datasheet PDF : 12 Pages
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HSP48410
Delay and Subtract Mode
This mode is similar to the Delay Memory mode, except the
input data is subtracted from the corresponding data stored
in RAM (See Figures 12 and 13).
DIN 0-23
CLK
RAM
IN OUT
ADDRESS
Σ
TWO’S
COMPLEMENT
COUNTER
DIO DIO 0-23
I/F
RD
START
CONTROL
FIGURE 12. DELAY AND SUBTRACT BLOCK DIAGRAM
The difference between the Async 16 mode and the Async
24 mode is the number of data bits available to the user. In
16-bit mode, the user can connect the system data bus to
the lower 16 bits of the Histogrammer’s DIO bus. The UWS
pin becomes the LSB of the IO address, which determines if
the lower 16 bits or upper 8 bits of the 24-bit Histogrammer
data is being used. When UWS is low, the data present at
DIO0-15 is the lower 16 bits of the data in the IOADD0-9
location. When UWS is high, the upper 8 bits of the
IOADD09 location are present on DIO0-7. (This is true for
both reading and writing). Thus, it takes 2 cycles for an
asynchronous 24-bit operation when in Async 16 mode.
Unused outputs are zeros.
24x1024
RAM
IN
OUT
WR
ADDRESS
DIO DIO 0-23
I/F
CLK
START
DATA
DIN 0-23
1
2 3 4 5 6 7 8 9 10 11 12 13 14
OUTPUT
DIO 0-23
MODIFIED DATA
1234 5
DATA 1
MINUS
DATA 7
DATA 2
MINUS
DATA 8
FIGURE 13. DELAY AND SUBTRACT MODE TIMING FOR ROW
LENGTH OF TEN
Asynchronous 16/24 Modes
In the Asynchronous modes, the chip acts like a single port
RAM. In this mode, the user can read (access) any bin
location on the fly by simply setting the 10-bit IO address to
the desired bin location. The RAM is then read or written on
the following RD or WR pulse. A block diagram for this mode
is shown in Figure 14. Note that all registers and pipeline
stages are bypassed; START and CLK have no effect in
this mode.
Timing waveforms for this mode are also shown in Figure 15.
During reading, the read address is latched (internally) on
the falling edge of RD. During write operations, the address
is latched on the falling edge of WR and data is latched on
the rising edge of WR. Note that reading and writing occur
on different ports, so that, in this mode, the write port always
latches its address and data values from the WR signal,
while the read port always uses RD for latching.
IOADD 0-9
ADDRESS
GENERATOR
WR
RD
UWS
CONTROL
FIGURE 14. ASYNCHRONOUS 16/24 BLOCK DIAGRAM
WRITE CYCLE TIMING
WR
RD
IOADD 0-9,
UWS
DIO 0-23
READ CYCLE TIMING
WR
RD
IOADD 0-9,
UWS
DIO 0-23
FIGURE 15. ASYNCHRONOUS 16/24 MODE TIMING
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