HSP48410 데이터 시트보기 (PDF) - Intersil
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HSP48410 Datasheet PDF : 12 Pages
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HSP48410
Look Up Table Mode
A Look Up Table (LUT) is used to perform a fixed
transformation function on pixel values. This is particularly
useful when the transformation is nonlinear and cannot be
realized directly with hardware. An example is the remapping
of the original pixel values to a new set of values based on
the CDF obtained through Histogram Accumulation.
The transformation function can be loaded into the LUT in
one of three ways: in LUT mode, through DIN0-23; in either
asynchronous mode, over the DIO bus as described below
under Asynchronous 16/24 Modes; in the Histogram
Accumulate mode the transformation function is calculated
internally (see description above). The transformation
function can then be utilized by deactivating START, putting
the part in LUT mode and clocking the data to be
transformed onto the PIN bus. Note that it is necessary to
wait one clock cycle after changing the mode before clocking
data into the part.
The Block Diagram and Timing Diagram for this mode are
shown in Figures 8 and 9. The left half of the timing diagram
shows LUT(write) mode. On the first CLK that detects
START low, the counter is reset and the write enable is
activated for the RAM. As long as START remains low, the
counter provides the write address to the RAM and data is
sequentially loaded through the DIN bus. The DIN bus is
delayed internally by 3 cycles to match the latency in the
Address Generator. The DIO bus will contain the previous
contents of the memory location being updated. When 1024
words have been written to the RAM, the counter stops and
further writes to the RAM are disabled. The part stays in this
state while START remains low.
When START returns high, the RAM write is disabled, the
read address is taken from the PIN bus, and the chip acts as
a synchronous LUT. (This is known as LUT(read) mode.) In
order to ensure that the internal pipelines are clear, data
should not be input to PIN0-9 until the third clock after
START goes high
DIN 0-23
RAM
IN
OUT
WR
ADDRESS
DIO DIO 0-23
Σ
I/F
PIN 0-9
ADDRESS
“0”
RD
GENERATOR
CLK
COUNTER
START
CONTROL
FIGURE 8. LOOK UP TABLE BLOCK DIAGRAM
CLK
START
(WRITE)
DATA
DIN 0-23 0 1 2 3 4 5
PIN 0-9
DIO 0-23
OUTPUT
0* 1* 2* 3*
(READ)
ADDRESS
0 1 23
0
* PREVIOUS CONTENTS OF BIN LOCATION.
FIGURE 9. LOOK UP TABLE MODE TIMING
Delay Memory (Row Buffer) Mode
As seen by comparing Figures 8 and 10, the configuration
for this mode is nearly identical to the LUT mode. In this
mode, however, the counter is always providing the address
and the write function is always enabled.
In order to force this configuration to act as a row delay
register, the START signal must be used to reset the internal
counter each time a new row of pixels is being sampled.
Because of the inherent latency in the address and data
paths, the counter must be reset every N-4 cycles, where N
is the desired delay length. For example, if a delay from DIN
to DIO of ten cycles is desired, the START signal must be set
low every six cycles (see Figure 11). If the internal address
counter reaches its maximum count (1023), it holds that
value and further writes to the RAM are disabled.
DIN 0-23
CLK
RAM
IN
OUT
ADDRESS
Σ
COUNTER
“0”
START
CONTROL
DIO DIO 0-23
I/F
RD
FIGURE 10. DELAY MEMORY BLOCK DIAGRAM
CLK
START
DATA
DIN 0-23 1 2 3 4 5 6 7 8 9 10 11 12 13 14
DIO 0-23
12345
FIGURE 11. DELAY MEMORY MODE TIMING FOR ROW
LENGTH OF TEN
8
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