HMN28D-70 데이터 시트보기 (PDF) - Hanbit Electronics Co.,Ltd

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HMN28D-70

Non-Volatile SRAM MODULE 16Kbit (2K x 8-Bit), 24pin DIP, 5V

Hanbit Electronics Co.,Ltd 

HANBit

HMN28D

- WRITE CYCLE NO.2 (/CE-Controlled)*1,2,3,4,5

tWC

Address

tAW

tAS

tCW

tWR2

/CE

/WE

DIN

DOUT

tWP

tWZ

Data Undefined (2)

tDW

tDH2

Data-in Valid

High-Z

NOTE: 1. /CE or /WE must be high during address transition.

2. Because I/O may be active (/OE low) during this period, data input signals of opposite

polarity to the outputs must not be applied.

3. If /OE is high, the I/O pins remain in a state of high impedance.

4. Either tWR1 or tWR2 must be met.

5. Either tDH1 or tDH2 must be met.

- POWER-DOWN/POWER-UP TIMING

tPF

VCC

4.75

VPFD

4.25

VSO

VPFD

VSO

tFS

tWPT

tDR

tPU

tCER

/CE

URL : www.hbe.co.kr

Rev. 0.0 (April, 2002)

8

HANBit Electronics Co.,Ltd

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