HMN28D-70 데이터 시트보기 (PDF) - Hanbit Electronics Co.,Ltd
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HMN28D-70 Datasheet PDF : 9 Pages
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HANBit
POWER-DOWN/POWER-UP CYCLE (TA= TOPR, VCC=5V)
PARAMETER
SYMBOL
CONDITIONS
MIN
VCC slew, 4.75 to 4.25V
tPF
300
VCC slew, 4.75 to VSO
tFS
10
VCC slew, VSO to VPFD (max)
tPU
0
Time during which SRAM
Chip enable recovery time
tCER
is write-protected after VCC
40
passes VPFD on power-up.
Data-retention time in
Absence of VCC
Data-retention time in
Absence of VCC
tDR
tDR-N
TA = 25℃
10
TA = 25℃ ; industrial
6
temperature range (-N) only
Write-protect time
Delay after VCC slews down
tWPT
past VPFD before SRAM is
40
Write-protected.
HMN28D
TYP.
-
-
-
MAX
-
-
-
UNIT
㎲
㎲
㎲
80
120
ms
-
-
years
-
-
years
100
150
㎲
TIMING WAVEFORM
- READ CYCLE NO.1 (Address Access)*1,2
Address
DOUT
tRC
tACC
tOH
Previous Data Valid
Data Valid
- READ CYCLE NO.2 (/CE Access)*1,3,4
tRC
/CE
DOUT
tACE
tCLZ
High-Z
tCHZ
High-Z
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
6
HANBit Electronics Co.,Ltd
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