HIP6302 데이터 시트보기 (PDF) - Intersil

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HIP6302

Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller

Intersil 

Simplified Power System Diagram

HIP6302

VSEN

PWM 1

HIP6302

PWM 2

VID

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

SYNCHRONOUS

RECTIFIED BUCK

CHANNEL

MICROPROCESSOR

Functional Pin Description

VID4 1

VID3 2

VID2 3

VID1 4

VID0 5

COMP 6

FB 7

FS/DIS 8

16 VCC

15 PGOOD

14 ISEN1

13 PWM1

12 PWM2

11 ISEN2

10 VSEN

9 GND

VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4)

and VID0 (Pin 5)

Voltage Identification inputs from microprocessor. These pins

respond to TTL and 3.3V logic signals. The HIP6302 decodes

VID bits to establish the output voltage. See Table 1.

COMP (Pin 6)

Output of the internal error amplifier. Connect this pin to the

external feedback and compensation network.

FB (Pin 7)

Inverting input of the internal error amplifier.

FS/DIS (Pin 8)

Channel frequency, FSW, select and disable. A resistor from

this pin to ground sets the switching frequency of the

converter. Pulling this pin to ground disables the converter

and three states the PWM outputs. See Figure 10.

3

GND (Pin 9)

Bias and reference ground. All signals are referenced to this

pin.

VSEN (Pin 10)

Power good monitor input. Connect to the microprocessor-

CORE voltage.

ISEN2 (Pin 11) and ISEN1 (Pin 14)

Current sense inputs from the individual converter channel’s

phase nodes.

PWM2 (Pin 12) and PWM1 (Pin 13)

PWM outputs for each driven channel in use. Connect these

pins to the PWM input of a HIP6601/2/3 driver.

PGOOD (Pin 15)

Power good. This pin provides a logic-high signal when the

microprocessor CORE voltage (VSEN pin) is within specified

limits and Soft-Start has timed out.

VCC (Pin 16)

Bias supply. Connect this pin to a 5V supply.

FN4766.3

December 27, 2004

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