HIP2122 데이터 시트보기 (PDF) - Intersil

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HIP2122

100V, 2A Peak, High Frequency Half-Bridge Drivers with Rising Edge Delay Timer

Intersil 

HIP2122, HIP2123

Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, RDT = 0kΩ, No Load on LO or HO, Unless Otherwise Specified.

PARAMETERS

(see “Timing Diagram”)

SYMBOL

TEST

CONDITIONS

TJ = +25°C

MIN TYPE MAX

TJ = -40°C to +125°C

MIN

(Note 9)

MAX

(Note 9)

UNITS

HO Turn-Off Propagation Delay

HI Falling to HO Falling

tPLHO

-

32 50

-

60

ns

LO Turn-Off Propagation Delay

LO Falling to LO Falling

tPLLO

-

32 50

-

60

ns

Minimum Dead-Time Delay (see Note 10)

HO Falling to LO Rising

tDTHLmin

RDT = 80k,

HI 1 to 0, LI 0 to 1

15

35

50

10

60

ns

Minimum Dead-Time Delay (see Note 10)

LO Falling to HO Rising

tDTLHmin

RDT = 80k

Li 1 to 0, HI 0 to 1

15

25

50

10

60

ns

Maximum Dead-Rising Delay (see Note 10)

HO Falling to LO rising

tDTHLmax

RDT = 8k,

HI 1 to 0, LI 0 to 1

150

220

300

-

-

ns

Maximum Dead-Time Delay (see Note 10)

LO Falling to HO Rising

tDTLHmax

RDT = 8k,

Li 1 to 0, HI 0 to 1

150

220

300

-

-

ns

Either Output Rise/Fall Time

(10% to 90%/90% to 10%)

tRC,tFC CL = 1nF

-

10

-

-

-

ns

Either Output Rise/Fall Time

(3V to 9V/9V to 3V)

tR,tF CL = 0.1mF

-

0.5 0.6

-

0.8

µs

Bootstrap Diode Turn-On or Turn-Off Time

tBS

-

10

-

-

-

ns

NOTES:

9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits are established by

characterization and are not production tested.

10. Dead-Time is defined as the period of time between the LO falling and HO rising or between HO falling and LO rising when the LI and HI inputs

transition simultaneously.

Timing Diagram

LI

LO

90%

HO 10%

HI

tR

EN

tDT

tPL

tDT

90%

10%

tPH

tF

tR AND tF FOR LO ARE NOT

SHOWN FOR CLARITY

7

FN7670.0

December 23, 2011

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