5962-9052501MQA 데이터 시트보기 (PDF) - Intersil

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5962-9052501MQA

CMOS Universal Asynchronous Receiver Transmitter (UART)

Intersil 

Switching Waveforms

HD-6402

TBR1 - TBR8 VALID DATA

CLS1, CLS2, SBS, PI, EPE

VALID DATA

SFD

RRD

TBRL

(4)

tSET

tPW

(2)

tHOLD

(5)

CRL

(4)

tSET

tPW

(2)

tHOLD

(5)

STATUS OR

RBR1 - RBR8

tEN

(6)

FIGURE 6. DATA INPUT CYCLE

FIGURE 7. CONTROL REGISTER LOAD

CYCLE

FIGURE 8. STATUS FLAG OUTPUT

ENABLE TIME OR DATA OUT-

PUT ENABLE TIME

A.C. Testing Input, Output Waveform

INPUT

VIH + 20% VIH

VIL - 50% VIL

1.5V

1.5V

OUTPUT

VOH

VOL

FIGURE 9.

NOTE: A.C. Testing: All input signals must switch between VIL - 50% VIL and VIH + 20% VIH. Input rise and fall times are driven at 1ns/V.

Test Circuit

OUT

CL

(SEE NOTE)

NOTE: Includes stray and jig capacitance, CL = 50pF.

FIGURE 10.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

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