5962-9052501MQA 데이터 시트보기 (PDF) - Intersil
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5962-9052501MQA Datasheet PDF : 7 Pages
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HD-6402
START BIT
5-8 DATA BITS
1, 11/2 OR 2 STOP BITS
LSB
MSB †
FIGURE 3. SERIAL DATA FORMAT
PARITY
† IF ENABLED
Start Bit Detection
The receiver uses a 16X clock timing. The start bit could have
occurred as much as one clock cycle before it was detected,
as indicated by the shaded portion (A). The center of the start
bit is defined as clock count 7 1/2. If the receiver clock is a
symmetrical square wave, the center of the start bit will be
located within ±1/2 clock cycle, ±1/32 bit or 3.125% giving a
receiver margin of 46.875%. The receiver begins searching
for the next start bit at the center of the first stop bit.
CLOCK
RRI INPUT
A
Interfacing with the HD-6402
START
71/2 CLOCK CYCLES
81/2 CLOCK CYCLES
FIGURE 4.
COUNT 71/2 DEFINED
CENTER OF START BIT
DIGITAL
SYSTEM
TRANSMITTER
TBR1
TBR8
TRO
CONTROL
HD-6402
CONTROL
RB1
RRI
RB8
RECEIVER
RS232
DRIVER
RS232
RECEIVER
RS232
RECEIVER
RS232
DRIVER
RECEIVER
RB1
RRI
RB8
CONTROL
HD-6402
CONTROL
TRO
TBR1
TBR8
TRANSMITTER
FIGURE 5. TYPICAL SERIAL DATA LINK
DIGITAL
SYSTEM
5
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