FAN5009 데이터 시트보기 (PDF) - Fairchild Semiconductor
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FAN5009 Datasheet PDF : 13 Pages
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FAN5009
PRODUCT SPECIFICATION
Circuit Description
The FAN5009 is a dual MOSFET driver optimized for driv-
ing N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side MOSFETs.
Each driver is capable of driving a 3nF load at speeds up to
500kHz.
For a more detailed description of the FAN5009 and its
features, refer to the Internal Block Diagram and Figure 1.
Low-Side Driver
The low-side driver (LDRV) is designed to drive a ground-
referenced low RDS(on) N-channel MOSFETs. The bias for
LDRV is internally connected between VCC and PGND.
When the driver is enabled, the driver’s output is 180° out of
phase with the PWM input. When the FAN5009 is disabled
(OD = 0V), LDRV is held low.
High-Side Driver
The high-side driver (HDRV) is designed to drive a floating
N-channel MOSFET. The bias voltage for the high-side
driver is developed by a bootstrap supply circuit, consisting
of the internal diode and external bootstrap capacitor
(CBOOT) .
During start-up, SW is held at PGND, allowing CBOOT to
charge to VCC through the internal diode. When the PWM
input goes high, HDRV will begin to charge the high-side
MOSFET’s gate (Q1). During this transition, charge is
removed from CBOOT and delivered to Q1’s gate. As Q1
turns on, SW rises to VIN, forcing the BOOT pin to
VIN +VC(BOOT), which provides sufficient VGS enhancement
for Q1.
To complete the switching cycle, Q1 is turned off by pulling
HDRV to SW. CBOOT is then recharged to VCC when SW
falls to PGND.
HDRV output is in phase with the PWM input. When the
driver is disabled, the high-side gate is held low.
Adaptive Gate Drive Circuit
The FAN5009 embodies an advanced design that ensures
minimum MOSFET dead-time while eliminating potential
shoot-through (cross-conduction) currents. It senses the
state of the MOSFETs and adjusts the gate drive, adaptively,
to ensure they do not conduct simultaneously. Refer to
Figure 4 for the relevant timing waveforms.
To prevent overlap during the low-to-high switching transi-
tion (Q2 OFF to Q1 ON), the adaptive circuitry monitors the
voltage at the LDRV pin. When the PWM signal goes
HIGH, Q2 will begin to turn OFF after some propagation
delay (tpdl(LDRV)).
Once the LDRV pin is discharged below ~1.2V, Q1 begins to
turn ON after adaptive delay tpdh(HDRV).
To preclude overlap during the high-to-low transition (Q1
OFF to Q2 ON), the adaptive circuitry monitors the voltage
at the SW pin. When the PWM signal goes LOW, Q1 will
begin to turn OFF after some propagation delay (tpdl(HDRV)).
Once the SW pin falls below ~2.2V, Q2 begins to turn ON
after adaptive delay tpdh(LDRV).
Additionally, VGS of Q1 is monitored. When VGS(Q1) is
discharged below ~1.2V, a secondary adaptive delay is initi-
ated, which results in Q2 being driven ON after tpdh(ODRV),
regardless of SW state. This function is implemented to
ensure CBOOT is recharged each switching cycle, particularly
for cases where the power convertor is sinking current and
SW voltage does not fall below the 2.2V adaptive threshold.
Secondary delay tpdh(ODRV) is longer than tpdh(LDRV).
Application Information
Supply Capacitor Selection
For the supply input (VCC) of the FAN5009, a local ceramic
bypass capacitor is recommended to reduce the noise and to
supply the peak current. Use at least a 1µF, X7R or X5R
capacitor. Keep this capacitor close to the FAN5009 VCC
and PGND pins.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBOOT) and the internal diode, as shown in Figure 1. Selec-
tion of these components should be done after the high-side
MOSFET has been chosen. The required capacitance is
determined using the following equation:
CBOOT = ∆-----V---Q-B---OG----O----T-
(1)
where QG is the total gate charge of the high-side MOSFET,
and ∆VBOOT is the voltage droop allowed on the high-side
MOSFET drive. For example, the QG of the FDD6696 is
about 35nC @ 12VGS. For an allowed droop of ~300mV, the
required bootstrap capacitance is 100nF. A good quality
ceramic capacitor must be used.
The average diode forward current, IF(AVG), can be
estimated by:
IF(AVG) = QGATE × FSW
(2)
where FSW is the switching frequency of the controller.
The peak surge current rating of the internal diode should be
checked in-circuit, since this is dependent on the equivalent
impedance of the entire bootstrap circuit, including the PCB
traces. For applications requiring higher IF, an external
diode may be used in parallel to the internal diode.
8
REV. 1.0.5 7/22/04
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