EP9312 데이터 시트보기 (PDF) - Cirrus Logic

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EP9312

Universal Platform System-on-chip Processor

Cirrus Logic 

Static Memory Single Word Read Cycle

Parameter

AD setup to CSn assert time

AD hold from CSn deassert time

RDn assert time

CSn to RDn delay time

CSn assert to DQMn assert delay time

DA setup to RDn deassert time

DA hold from RDn deassert time

Symbol

tADs

tADh

tRDpw

tRDd

tDQMd

tDAs

tDAh

See “Timing Conditions” on page 14 for definition of HCLK.

Min

0

tHCLK

-

-

-

tHCLK + 12

0

EP9312

Universal Platform SOC Processor

Typ

-

-

tHCLK × (WST1 + 2)

-

-

-

-

Max

-

-

-

3

1

-

-

Unit

ns

ns

ns

ns

ns

ns

ns

AD

CSn

WRn

RDn

DQMn

DA

WAIT

tADs

tADh

tRDd

tDQMd

tRDd

tDAs

tDAh

Figure 6. Static Memory Single Word Read Cycle Timing Measurement

DS515PP7

©Copyright 2005 Cirrus Logic (All Rights Reserved)

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