EP9312 데이터 시트보기 (PDF) - Cirrus Logic

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EP9312

Universal Platform System-on-chip Processor

Cirrus Logic 

EP9312

Universal Platform SOC Processor

Memory Interface

Figure 2 through Figure 5 define the timings associated with all phases of the SDRAM. The following table contains the

values for the timings of each of the SDRAM modes.

Parameter

SDCLK high time

SDCLK low time

SDCLK rise/fall time

Signal delay from SDCLK rising edge time

Signal hold from SDCLK rising edge time

DQMn delay from SDCLK rising edge time

DQMn hold from SDCLK rising edge time

DA valid setup to SDCLK rising edge time

DA valid hold from SDCLK rising edge time

Symbol

tclk_high

tclk_low

tclkrf

td

th

tDQd

tDQh

tDAs

tDAh

Min

Typ

Max

-

(tHCLK) / 2

-

-

(tHCLK) / 2

-

-

2

4

-

-

8

1

-

-

-

-

8

1

-

-

2

-

-

3

-

-

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

SDRAM Load Mode Register Cycle

tclkrf

SDCLK

td

SDCSn

RASn

CASn

SDWEn

DQMn

AD

DA

tclk_low

tclk_high

th

OP-Code

Figure 2. SDRAM Load Mode Register Cycle Timing Measurement

DS515PP7

©Copyright 2005 Cirrus Logic (All Rights Reserved)

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