EN25F05 데이터 시트보기 (PDF) - Eon Silicon Solution Inc.

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EN25F05

512 Kbit Serial Flash Memory with 4Kbytes Uniform Sector

Eon Silicon Solution Inc. 

EN25F05

Figure 13 Block Erase Instruction Sequence Diagram

Chip Erase (CE) (C7h/60h)

The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable

(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction

has been decoded, the device sets the Write Enable Latch (WEL).

The Chip Erase (CE) instruction is entered by driving Chip Select (CS#) Low, followed by the

instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire

duration of the sequence.

The instruction sequence is shown in Figure 14. Chip Select (CS#) must be driven High after the

eighth bit of the instruction code has been latched in, otherwise the Chip Erase instruction is not

executed. As soon as Chip Select (CS#) is driven High, the self-timed Chip Erase cycle (whose

duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be

read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time

before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

The Chip Erase (CE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The

Chip Erase (CE) instruction is ignored if one, or more, sectors are protected.

Figure 14. Chip Erase Instruction Sequence Diagram

This Data Sheet may be revised by subsequent versions 16 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

Rev. B, Issue Date: 2008/06/23

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