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DSP56307UM

24-BIT DIGITAL SIGNAL PROCESSOR

Motorola => Freescale 

Signals/Connections

External Memory Expansion Port (Port A)

External Data Bus

Signal

Name

D0ÐD23

Type

Input/

Output

Table 1-7 External Data Bus Signals

State During

Reset

Signal Description

Tri-stated

Data BusÑWhen the DSP is the bus master,

D0ÐD23 are active-high, bidirectional

input/outputs that provide the bidirectional data

bus for external program and data memory

accesses. Otherwise, D0ÐD23 are tri-stated. These

lines have weak keepers to maintain the last state

even if all drivers are tri-stated.

External Bus Control

Table 1-8 External Bus Control Signals

Signal

Name

AA0ÐAA3

Type

State During

Reset

Signal Description

Output Tri-stated

Address AttributeÑWhen defined as AA, these signals

can be used as chip selects or additional address lines.

The default use defines a priority scheme under which

only one AA signal can be asserted at a time. Setting the

AA priority disable (APD) bit (Bit 14) of the OMR, the

priority mechanism is disabled and the lines can be

used together as four external lines that can be decoded

externally into 16 chip select signals.

RAS0ÐRAS3 Output

RD

Output Tri-stated

WR

Output Tri-stated

Row Address StrobeÑWhen defined as RAS, these

signals can be used as RAS for DRAM interface. These

signals are tri-statable outputs with programmable

polarity.

Read EnableÑWhen the DSP is the bus master, RD is

an active-low output that is asserted to read external

memory on the data bus (D0ÐD23). Otherwise, RD is

tri-stated.

Write EnableÑWhen the DSP is the bus master, WR is

an active-low output that is asserted to write external

memory on the data bus (D0ÐD23). Otherwise, the

signals are tri-stated.

Not Recommended for New Design

MOTOROLA

DSP56307 Technical Data

1-7

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