DM9003
2-port Switch with Processor Interface
3. FEATURES
Ethernet Switch with two 10/100Mbps PHYs and general processor bus interface
Processor bus slave architecture
EEPROM interface for power-up configuration
TCP/UDP/IPv4 checksum offload
Support HP Auto-MDIX
IEEE 802.3x Flow Control in Full-duplex mode
Back Pressure Flow Control in Half-duplex mode
Each port supports 4 priority queues by Port-based, 802.1P QoS, and IP TOS priority
Support 802.1Q VLAN up to 16 VLAN groups
Support VLAN ID tag/untag option
Each port supports bandwidth, ingress and egress rate control
Support Broadcast Storming filter function
Support Store and Forward switching approach
Support up to 1K uni-cast MAC addresses
Automatic aging scheme
Support MIB counters for diagnostic
uP data driving capability adjustable
64-pin LQFP 1.8V internal core, 3.3V I/O with 5V tolerant
10
Preliminary datasheet
DM9003-15-DS-P05
April 9, 2009