DG508ACJZ 데이터 시트보기 (PDF) - Intersil

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DG508ACJZ

CMOS Analog Multiplexers

Intersil 

DG508A

Functional Diagram

DG508A

S1

S2

S3

S4

D

S5

ADDRESS DECODER

S6

1 OF 8

S7

S8

A0 A1 A2 EN (ENABLE INPUT)

3 Line Binary Address Inputs

(1 0 1) and EN = 1

Above example shows channel 6 turned ON.

Schematic Diagram

V+

LOGIC TRIP

POINT REF

GND

LOGIC AX

INPUT OR EN

V-

LOGIC INTERFACE

AND LEVEL SHIFTER

DECODER

+

-

AX

V+

SX

DX

TYPICAL

SWITCH

2

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