QL5732-33BPT280M 데이터 시트보기 (PDF) - QuickLogic Corporation

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QL5732-33BPT280M

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5732 Enhanced QuickPCI Device Data Sheet Rev. E

Table 1: PCI Master Interface

Signal

I/O

Description

Mst_Two_Reads I

Mst_RdData_Valid O

Mst_RdBurst_Done O

Flush_FIFO

I

Mst_LatCntEn

I

Mst_Xfer_D1

O

Mst_Last_Cycle O

Mst_REQN

O

Mst_IRDYN

O

Two data transfers remain to be read in the burst Read It is not used for single-data-phase

Master Read transactions.

Master Read data valid on Usr_Addr_WrData[31:0] This serves as the PUSH control for the

external FIFO (in FPGA region) that receives data from the PCI32 core.

Master Read transaction is completed Active for only one clock cycle.

Internal FIFO flush FIFO flushed immediately after it is active (synchronized with PCI clock).

Enable Latency Counter Set to 0 to ignore the Latency Timer in the PCI configuration space

(offset 0Ch).

For full PCI compliance, this port should be always set to 1.

Data was transferred on the previous PCI clock Useful for updating DMA transfer counts on

DMA Read operations

Active during the last data transfer of a master transaction

Copy of the PCI REQN signal generated by QL5732 as PCI master Not usually used in

the back-end design.

Copy of the PCI IRDYN signal generated by QL5732 as PCI master Valid only when

QL5732 is the PCI master. Kept low otherwise. Not usually used in the back-end design.

Mst_Tabort_Det

Mst_TTO_Det

O Target abort detected during master transaction This is normally an error condition handled

in the DMA controller.

O Target timeout detected (no response from target) This is normally an error condition

handled in the DMA controller.

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