QL5732 Enhanced QuickPCI
Device Data Sheet
• • • • • • 33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and
Dual Port SRAM
Device Highlights
High Performance PCI Controller
• 32-bit/33 MHz PCI Master/Target
• Zero-wait state PCI Master provides
132 MBps transfer rates
• Zero-wait-state PCI Target Write/One-wait-state
PCI Target Read interface
• Supports all PCI commands, including
configuration and MWI
• Supports fully-customizable byte enable for
master channels
• Target interface supports retry, disconnect
with/without data transfer, and target abort
• Fully programmable back-end interface
• Independent PCI bus (33 MHz) and local bus (up
to 160 MHz) clocks
• Fully customizable PCI Configuration Space
• Configurable FIFOs with depths up to 256 words
• Reference design with driver code
(Win 95/98/Win 2000/NT4.0) available
• PCI v2.3 compliant
• Supports Type 0 Configuration Cycles in Target
mode
• 3.3 V PCI signaling
• 2.5 V Supply Voltage
• 484-ball PBGA
• 280-ball LFBGA
• 208-pin PQFP
• Supports Extendable PCI functionality
• Unlimited/Continuous Burst Transfers supported
Flexible Programmable Logic
• 1,348 Logic Cells
• 50,688 RAM bits
• Up to 262 I/O pins
• All back-end interface and glue-logic can be
implemented on chip
• Six 32-bit busses interface between the PCI
Controller and the Programmable Logic
• Twenty-two 2,304 bit Dual Port High
Performance SRAM Blocks
• 3,482 flip-flops available
PCI Bus 33 MHz/32 bits (data and address)
Master
Controller
High
Speed
Data
Path
Target
Controller
32 bit Interface
Programmable
Logic
262/115 User I/O 160 MHz
FIFOs
High Speed
Logic Cells
Config
space
DMA
Controller
Figure 1: 5732 Block Diagram
Extendable PCI Functionality
• Support for PCI host-bridge function
• Support for Configuration Space from
0 × 40 to 0 × 3FF
• Multi-Function, Expanded Capabilities, and
Expansion ROM capable
• PCI v2.3 Power Management Spec compatible
• PCI v2.3 Vital Product Data (VPD) configuration
support
© 2003 QuickLogic Corporation
•
www.quicklogic.com
•
•
1
•
•
•