CY7C43642AV 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C43642AV

3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO

Cypress Semiconductor 

CY7C43642AV

CY7C43662AV

CY7C43682AV

Pin Definitions (continued)

Signal Name Description

MRST2

FIFO2 Master

Reset

RT1

RT2

W/RA

W/RB

Retransmit

FIFO1

Retransmit

FIFO2

Port A

Write/Read

Select

Port B

Write/Read

Select

I/O

Function

I A LOW on this pin initializes the FIFO2 Read and Write pointers to the first location of

memory and sets the Port A output register to all zeroes. A LOW pulse on MRST2

selects one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH

transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while

MRST2 is LOW.

I A LOW strobe on this pin will retransmit the data on FIFO1. This is achieved by bringing

the Read pointer back to location zero. The user will still need to perform Read opera-

tions to retransmit the data. Retransmit function applies to CY standard mode only.

I A LOW strobe on this pin will retransmit the data on FIFO2. This is achieved by bringing

the Read pointer back to location zero. The user will still need to perform Read opera-

tions to retransmit the data. Retransmit function applies to CY standard mode only.

I A HIGH selects a Write operation and a LOW selects a Read operation on Port A for a

LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the high-impedance state

when W/RA is HIGH.

I A LOW selects a Write operation and a HIGH selects a Read operation on Port B for a

LOW-to-HIGH transition of CLKB. The B0–35 outputs are in the high-impedance state

when W/RB is LOW.

Document #: 38-06020 Rev. *C

Page 5 of 30

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