CY7C43642AV 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C43642AV Datasheet PDF : 30 Pages
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CY7C43642AV
CY7C43662AV
CY7C43682AV
Pin Definitions (continued)
Signal Name Description
CLKA
Port A Clock
CLKB
Port B Clock
CSA
CSB
EFA/ORA
EFB/ORB
ENA
ENB
FFA/IRA
Port A Chip
Select
Port B Chip
Select
Port A Empty/
Output Ready
Flag
Port B Empty/
Output Ready
Flag
Port A Enable
Port B Enable
Port A Full/Input
Ready Flag
FFB/IRB
Port B Full/Input
Ready Flag
FS1
FS0
MBA
MBB
MBF1
Flag Offset
Select 1
Flag Offset
Select 0
Port A Mailbox
Select
Port B Mailbox
Select
Mail1 Register
Flag
MBF2
Mail2 Register
Flag
MRST1
FIFO1 Master
Reset
I/O
Function
I CLKA is a continuous clock that synchronizes all data transfers through Port A and can
be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all
synchronized to the LOW-to-HIGH transition of CLKA.
I CLKB is a continuous clock that synchronizes all data transfers through Port B and can
be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all
synchronized to the LOW-to-HIGH transition of CLKB.
I CSA must be LOW to enable a LOW-to HIGH transition of CLKA to Read or Write on
Port A. The A0–35 outputs are in the high-impedance state when CSA is HIGH.
I CSB must be LOW to enable a LOW-to HIGH transition of CLKB to Read or Write on
Port B. The B0–35 outputs are in the high-impedance state when CSB is HIGH.
O This is a dual-function pin. In the CY Standard mode, the EFA function is selected.
EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is selected. ORA indicates the presence of valid data on A0–35 outputs available
for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.
O This is a dual-function pin. In the CY Standard mode, the EFB function is selected.
EFB indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is selected. ORB indicates the presence of valid data on B0–35 outputs available
for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.
I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to Read or Write data
on Port A.
I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to Read or Write data
on Port B.
O This is a dual-function pin. In the CY Standard mode, the FFA function is selected.
FFA indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA
function is selected. IRA indicates whether or not there is space available for writing to
the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
O This is a dual-function pin. In the CY Standard mode, the FFB function is selected.
FFB indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB
function is selected. IRB indicates whether or not there is space available for writing to
the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.
I The LOW-to-HIGH transition of a FIFO’s reset input latches the values of FS0 and FS1.
If either FS0 or FS1 is HIGH when a reset input goes HIGH, one of the three preset
I
values (8, 16, or 64) is selected as the offset for the FIFO’s Almost Full and Almost
Empty flags. If both FIFOs reset simultaneously and both FS0 and FS1 are LOW when
MRST1 and MRST2 go HIGH, the first four Writes program the Almost Empty and
Almost Full offsets for both FIFOs.
I A HIGH level on MBA chooses a mailbox register for a Port A Read or Write operation.
When the A0–35 outputs are active, a HIGH level on MBA selects data from the Mail2
register for output and a LOW level selects FIFO2 output register data for output.
I A HIGH level on MBB chooses a mailbox register for a Port B Read or Write operation.
When the B0–35 outputs are active, a HIGH level on MBB selects data from the Mail1
register for output and a LOW level selects FIFO1 output register data for output.
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH
by a LOW-to-HIGH transition of CLKB when a Port B Read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH
by a LOW-to-HIGH transition of CLKA when a Port A Read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
I A LOW on this pin initializes the FIFO1 Read and Write pointers to the first location of
memory and sets the Port B output register to all zeroes. A LOW pulse on MRST1
selects the programming method (serial or parallel) and one of three programmable flag
default offsets for FIFO1. Four LOW-to-HIGH transitions of CLKA and four
LOW-to-HIGH transitions of CLKB must occur while MRST1 is LOW.
Document #: 38-06020 Rev. *C
Page 4 of 30
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