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CY7C4364 Datasheet PDF : 40 Pages
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CY7C43646AV
CY7C43666AV
CY7C43686AV
Functional Description
The CY7C436X6AV is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous FIFO memory that supports
clock frequencies up to 133 MHz and has Read access times
as fast as 6 ns. Two independent 1K/4K/16K × 36 dual-port
SRAM FIFOs on board each chip buffer data in opposite direc-
tions.
The CY7C436X6AV is a synchronous (clocked) FIFO,
meaning each port employs a synchronous interface. All data
transfers through a port are gated to the LOW-to-HIGH
transition of a port clock by enable signals. The clocks for each
port are independent of one another and can be asynchronous
or coincident. The enables for each port are arranged to
provide a simple bidirectional interface between micropro-
cessors and/or buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers’ width matches
the selected Port B or Port C bus width. Each mailbox register
has a flag (MBF1 and MBF2) to signal when new mail has
been stored. Two kinds of reset are available on the
CY7C436X6AV: Master Reset and Partial Reset. Master
Reset initializes the Read and Write pointers to the first
location of the memory array, configures the FIFO for Big or
Little Endian byte arrangement and selects serial flag
programming, parallel flag programming, or one of the three
possible default flag offset settings, 8, 16, or 64. Each FIFO
has its own independent Master Reset pin, MRS1 and MRS2.
Partial Reset also sets the Read and Write pointers to the first
location of the memory. Unlike Master Reset, any settings
existing prior to Partial Reset (i.e., programming method and
partial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings. Each FIFO has its own
independent Partial Reset pin, PRS1 and PRS2.
The CY7C436X6AV have two modes of operation CY
standard mode and FWFT mode: In the CY Standard mode,
the first word written to an empty FIFO is deposited into the
memory array. A Read operation is required to access that
word (along with all other words residing in memory). In the
First-Word Fall-Through Mode (FWFT), the first long-word
(36-bit wide) written to an empty FIFO appears automatically
on the outputs, no Read operation required (nevertheless,
accessing subsequent words does necessitate a formal Read
request). The state of the FWFT/STAN pin during FIFO
operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag
(EFA/ORA and EFB/ORB) and a combined Full/Input Ready
Flag (FFA/IRA and FFC/IRC). The EF and FF functions are
selected in the CY Standard mode. EF indicates whether the
memory is empty or not. FF indicates whether the memory is
full or not. The IR and OR functions are selected in the First
Word Fall-Through Mode. IR indicates whether or not the FIFO
has available memory locations. OR shows whether the FIFO
has data available for reading or not. It marks the presence of
valid data on the outputs.
Each FIFO has a programmable Almost Empty flag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFC).
AEA and AEB indicate when a selected number of words read
from the FIFO memory achieve a predetermined “almost
empty state.” AFA and AFC indicate when a selected number
of words written to the memory achieve a predetermined
“almost full state” (see note 61).
IRA, IRC, AFA, and AFC are synchronized to the port clock
that writes data into its array. ORA, ORB, AEA, and AEB are
synchronized to the port clock that reads data from its array.
Programmable offset for AEA, AEB, AFA, and AFC are loaded
in parallel using Port A or in serial via the SD input. Three
default offset settings are also provided. The AEA and AEB
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AFA and AFC threshold can be set at 8, 16, or
64 locations from the full boundary. All these choices are made
using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths. Such a width expansion requires no additional
external logic.
The CY7C436X6AV FIFOs are characterized for operation
from 0°C – 70°C commercial, and from –40°C – 85°C indus-
trial. Input ESD protection is greater than 2001V, and latch-up
is prevented by the use of guard rings.
Selection Guide
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-Up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply
Current (ICC1)
Commercial
Industrial
CY7C43646/66/86AV
–7
133
6
7.5
3
0
6
60
CY7C43646/66/86AV-
–10
100
8
10
4
0
8
60
CY7C43646/66/86AV
–15
66.7
10
15
5
0
10
60
60
Unit
MHz
ns
ns
ns
ns
ns
mA
Density
Package
CY7C43646AV
1K × 36/×18 ×2
128 TQFP
CY7C43666AV
4K × 36/×18 ×2
128 TQFP
CY7C43686AV
16K × 36/×18 ×2
128 TQFP
Document #: 38-06026 Rev. *C
Page 3 of 40
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