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CY7C4364 Datasheet PDF : 40 Pages
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CY7C43646AV
CY7C43666AV
CY7C43686AV
Register employs data lines C0–17. If the selected Port C bus
size is 9 bits, then the usable width of the Mail2 Register
employs data lines C0-8. (In this case, C9-17 are don’t care
inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted Writes to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register if the port Mailbox Select
input is LOW, and from the mail register if the port Mailbox
Select input is HIGH.
The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-
HIGH transition on CLKB when a Port B Read is selected by
CSB, RENB, and MBB HIGH. For a 18-bit bus size, 18 bits of
mailbox data are placed on B0–17. For a 9-bit bus size, 9 bits
of mailbox data are placed on B0–8. (In this case, B9–17 are
indeterminate.)
The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-
HIGH transition on CLKA when a Port A Read is selected by
CSA, W/RA, and ENA with MBA HIGH.
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizing
The Port B and Port C buses can be configured in a 18-bit word
or 9-bit byte format for data Read from FIFO1 or written to
FIFO2. The levels applied to the Port B Bus Size Select
(SIZEB) and the Port C Bus Size Select (SIZEC) determine
the width of the buses. The bus size can be selected indepen-
dently for Ports B and C. These levels should be static
throughout FIFO operation. Both bus-size selections are
implemented at the completion of Master Reset, by the time
the Full/Input Ready flag is set HIGH.
Two different methods for sequencing data transfer are
available for Port B when the bus size selection is either byte-
or word-size. They are referred to as Big Endian (most signif-
icant byte first) and Little Endian (least significant byte first).
The level applied to the Big Endian Select (BE) input during
the LOW-to-HIGH transition of MRS1 and MRS2 selects the
endian method that will be active during FIFO operation. The
endian method is implemented at the completion of Master
Reset, by the time the Full/Input Ready flag is set HIGH.
Only 36-bit long-word data is written to or read from Port A for
the CY7C436X6AV FIFO. Bus-matching operations are done
after data is read from the FIFO1 RAM and before data is
written to FIFO2 RAM. These bus-matching operations are not
available when transferring data via mailbox registers.
Furthermore, both the word- and byte-size bus selections limit
the width of the data bus that can be used for mail register
operations. In this case, only those byte lanes belonging to the
selected word- or byte-size bus can carry mailbox data. The
remaining data outputs will be indeterminate. The remaining
data inputs will be don’t care inputs. For example, when a
word-size bus is selected, then mailbox data can be trans-
mitted only between A0–17 and B0–17. When a byte-size bus is
selected, then mailbox data can be transmitted only between
A0–8 and B0–8.
Bus-Matching FIFO1 Reads
Data is written to the FIFO1 RAM in 36-bit long-word incre-
ments. If byte or word size is implemented on Port B, only the
first one or two bytes appear on the selected portion of the
FIFO1 output register, with the rest of the long-word stored in
auxiliary registers. In this case, subsequent FIFO1 reads
output the rest of the long word to the FIFO1 output register.
When reading data from FIFO1 as byte, the unused B9–17
outputs are indeterminate.
Bus-Matching FIFO2 Writes
Data is written to the FIFO2 RAM in 18-bit word increments.
Data written to FIFO2 with a byte or word bus size stores the
initial bytes or words in auxiliary registers. The CLKC rising
edge that writes the word to FIFO2 also stores the entire long-
word in FIFO2 RAM.
When writing data into FIFO2 in byte format, the unused C8–17
inputs will be don’t care inputs.
Retransmit (RT1, RT2)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Retransmit
function applies to CY standard mode only.
The number of 36-/18-/9-bit words written into the FIFO should
be less than full depth minus 2/4/8 words between the reset of
the FIFO (master or partial) and Retransmit setup. A LOW
pulse on RT1, (RT2) resets the internal Read pointer to the first
physical location of the FIFO. CLKA CLKB and CLKC may be
free running but RENB (ENA) must be disabled during and
tRTR after the retransmit pulse. With every valid Read cycle
after retransmit pulse, previously accessed data is read and
the Read pointer can be incremented until it is equal to the
Write pointer. Flags are governed by the relative locations of
the Read and Write pointers and are updated during a retrans-
mit cycle. Data written to the FIFO after activation of RT1,
(RT2) are transmitted also. The full depth of the FIFO can be
repeatedly retransmitted.
Document #: 38-06026 Rev. *C
Page 10 of 40
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