CY7C4205V 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C4205V Datasheet PDF : 20 Pages
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CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
Selection Guide
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Operating Current
Commercial
CY7C42X5V-15
66.7
11
15
4
1
11
30
CY7C42X5V-25
40
15
25
6
1
15
30
CY7C42X5V-35
28.6
20
35
7
2
20
30
Unit
MHz
ns
ns
ns
ns
ns
mA
Density
Packages
CY7C4425V
64 x 18
64-pin 14x14
TQFP
64-pin 10x10
STQFP
CY7C4205V
256 x 18
64-pin 14x14
TQFP
64-pin 10x10
STQFP
CY7C4215V
512 x 18
64-pin 14x14
TQFP
64-pin 10x10
STQFP
CY7C4225V
1K x 18
64-pin 14x14
TQFP
64-pin 10x10
STQFP
CY7C4235V
2K x 18
64-pin 14x14
TQFP
64-pin 10x10
STQFP
CY7C4245V
4K x 18
64-pin 14x14
TQFP
64-pin 10x10
STQFP
Pin Definitions
Signal Name Description
D0−17
Q0−17
WEN
Data Inputs
Data Outputs
Write Enable
REN
Read Enable
WCLK
Write Clock
RCLK
Read Clock
WXO/HF
EF
FF
PAE
Write Expansion
Out/Half Full Flag
Empty Flag
Full Flag
Programmable
Almost Empty
PAF
LD
FL/RT
Programmable
Almost Full
Load
First Load/
Retransmit
WXI
Write Expansion
Input
RXI
Read Expansion
Input
I/O
Function
I Data inputs for an 18-bit bus.
O Data outputs for an 18-bit bus.
I Enables the WCLK input.
I Enables the RCLK input.
I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is
not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is
not Empty. When LD is asserted, RCLK reads data out of the programmable
flag-offset register.
O Dual-Mode Pin. Single device or width expansion - Half Full status flag. Cascaded –
Write Expansion Out signal, connected to WXI of next device.
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty
offset value programmed into the FIFO. PAE is asynchronous when
VCC/SMODE is tied to VCC; it is synchronized to RCLK when VCC/SMODE is tied
to VSS.
O When PAF is LOW, the FIFO is almost full based on the almost full offset
value programmed into the FIFO. PAF is asynchronous when VCC/SMODE is
tied to VCC; it is synchronized to WCLK when VCC/SMODE is tied to VSS.
I When LD is LOW, D0−17 (O0−17) are written (read) into (from) the program-
mable-flag-offset register.
I Dual-Mode Pin. Cascaded – The first device in the daisy chain will have FL tied to
VSS; all other devices will have FL tied to VCC. In standard mode of width
expansion, FL is tied to VSS on all devices. Not Cascaded – Tied to VSS. Retransmit
function is also available in standalone mode by strobing RT.
I Cascaded – Connected to WXO of previous device. Not Cascaded – Tied to VSS.
I Cascaded – Connected to RXO of previous device. Not Cascaded – Tied to VSS.
Document #: 38-06029 Rev. *C
Page 3 of 20
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