CY7C4425-35AI 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C4425-35AI Datasheet PDF : 25 Pages
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CY7C4425/4205/4215
CY7C4225/4235/4245
Selection Guide
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Operating Current (ICC2) Commercial
(mA) @ freq=20MHz
Industrial
7C42X5-10
100
8
10
3
0.5
8
45
50
7C42X5-15
66.7
10
15
4
1
10
45
50
7C42X5-25
40
15
25
6
1
15
45
50
7C42X5-35
28.6
20
35
7
2
20
45
50
Density
Packages
CY7C4425
64 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4205
256 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4215
512 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4225
1K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4235
2K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4245
4K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
Pin Definitions
Signal Name Description I/O
Function
D0–17
Q0–17
WEN
Data Inputs
Data Outputs
Write Enable
I Data inputs for an 18-bit bus
O Data outputs for an 18-bit bus
I Enables the WCLK input
REN
Read Enable
I Enables the RCLK input
WCLK
Write Clock
I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK
Read Clock
I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-
set register.
WXO/HF
Write Expansion O Dual-Mode Pin:
Out/Half Full Flag
Single device or width expansion - Half Full status flag.
Cascaded - Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
O When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
Almost Empty
value programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied
to VCC; it is synchronized to RCLK when VCC/SMODE is tied to VSS.
PAF
Programmable
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
Almost Full
programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to
VCC; it is synchronized to WCLK when VCC/SMODE is tied to VSS.
LD
Load
I When LD is LOW, D0 - 17 (O0 - 17) are written (read) into (from) the programma-
ble-flag-offset register.
FL/RT
First Load/
Retransmit
I Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to VSS; all other
devices will have FL tied to VCC. In standard mode of width expansion, FL is tied
to VSS on all devices.
Not Cascaded - Tied to VSS. Retransmit function is also available in standalone
mode by strobing RT.
WXI
Write Expansion I Cascaded - Connected to WXO of previous device.
Input
Not Cascaded - Tied to VSS.
3
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