CY7C1346H 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1346H

2-Mbit (64K x 36) Pipelined Sync SRAM

Cypress Semiconductor 

CY7C1346H

Capacitance[10]

Parameter

Description

CIN

CCLK

CI/O

Input Capacitance

Clock Input Capacitance

Input/Output Capacitance

Thermal Resistance[10]

Test Conditions

TA = 25°C, f = 1 MHz,

VDD = 3.3V.

VDDQ = 2.5V

Parameter

ΘJA

ΘJC

Description

Thermal Resistance

(Junction to Ambient)

Thermal Resistance

(Junction to Case)

AC Test Loads and Waveforms

Test Conditions

Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA/JESD51

100 TQFP

Max.

5

5

5

100 TQFP

Package

30.32

6.85

Unit

pF

pF

pF

Unit

°C/W

°C/W

3.3V I/O Test Load

OUTPUT

Z0 = 50Ω

3.3V

OUTPUT

RL = 50Ω

5 pF

VL = 1.5V

(a)

INCLUDING

JIG AND

SCOPE

R = 317Ω

R = 351Ω

(b)

VDDQ

GND

ALL INPUT PULSES

10%

90%

≤ 1 ns

90%

10%

≤ 1 ns

(c)

2.5V I/O Test Load

OUTPUT

Z0 = 50Ω

2.5V

OUTPUT

RL = 50Ω

5 pF

VT = 1.25V

(a)

INCLUDING

JIG AND

SCOPE

R = 1667Ω

R =1538Ω

VDDQ

GND

ALL INPUT PULSES

10%

90%

≤ 1 ns

90%

10%

≤ 1 ns

(b)

(c)

Note:

10. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05672 Rev. *B

Page 9 of 16

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