CY7C135-15(2004) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C135-15
(Rev.:2004)

4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores

Cypress Semiconductor 

CY7C135

CY7C1342

Switching Waveforms (continued)

Semaphore Read After Write Timing, Either Side (CY7C1342 only)[22]

A0–A 2

VALID ADDRESS

tAA

VALID ADDRESS

tOHA

SEM

tAW

tSCE

tHA

tSOP

tACE

I/O0

R/W

tSD

DATAINVALID

tSA

tPWE

tHD

DATAOUT VALID

tSWRD

tDOE

OE

tSOP

WRITE CYCLE

READ CYCLE

Timing Diagram of Semaphore Contention (CY7C1342 only)[23,24,25]

1342–14

A0L–A 2L

MATCH

R/WL

SEML

A0R–A 2R

tSPS

MATCH

R/W R

SEM R

Notes:

22. CE = HIGH for the duration of the above timing (both write and read cycle).

23. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.

24. Semaphores are reset (available to both ports) at cycle start.

25. If tSPS is violated, it is guaranteed that only one side will gain access to the semaphore.

1342–15

Document #: 38-06038 Rev. *B

Page 8 of 12

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