CY7C135-15(2004) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C135-15
(Rev.:2004)

4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores

Cypress Semiconductor 

CY7C135

CY7C1342

Switching Waveforms (continued)

Write Cycle No. 1: OE Three-States Data I/Os (Either Port)[18,19,20]

ADDRESS

[13]

SEM

OR CE

R/W

tSA

DATAIN

tWC

tSCE

tAW

tPWE

tSD

DATA VALID

tHA

tHD

OE

DATAOUT

tHZOE

HIGH IMPEDANCE

Write Cycle No. 2:R/W Three-States Data I/Os (Either Port)[19, 21]

ADDRESS

SEM [13]

OR CE

R/W

tWC

tSCE

tSA

tAW

tPWE

tLZOE

1342–12

tHA

DATAIN

DATAOUT

tHZWE

tSD

tHD

DATA VALID

tLZWE

HIGH IMPEDANCE

1342–13

Notes:

18. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can

terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

19. R/W must be HIGH during all address transactions.

20. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the

bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified

tPWE.

21. Data I/O pins enter high-impedance when OE is held LOW during write.

Document #: 38-06038 Rev. *B

Page 7 of 12

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