CY7C130A 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C130A

1 K × 8 Dual-Port Static RAM

Cypress Semiconductor 

Switching Characteristics

Over the Operating Range[12, 13] (continued)

Parameter

Description

Busy/Interrupt Timing

tBLA

BUSY LOW from address match

tBHA

BUSY HIGH from address mismatch[20]

tBLC

tBHC

BUSY LOW from CE LOW

BUSY HIGH from CE HIGH[20]

tPS

tWB[21]

Port set-up for priority

R/W LOW after BUSY LOW

tWH

R/W HIGH after BUSY HIGH

tBDD

BUSY HIGH to valid data

tDDD

Write data valid to read data valid

tWDD

Write pulse to data delay

Interrupt Timing

tWINS

R/W to INTERRUPT set time

tEINS

CE to INTERRUPT set time

tINS

tOINR

tEINR

tINR

Address to INTERRUPT set time

OE to INTERRUPT reset time[20]

CE to INTERRUPT reset time[20]

Address to INTERRUPT reset time[20]

Shaded areas contain preliminary information.

CY7C130, CY7C130A

CY7C131, CY7C131A

7C131-15[14]

7C131A-15

7C141-15

Min Max

7C130-25[14]

7C131-25

7C140-25

7C141-25

Min Max

7C130-30

7C130A-30

7C131-30

7C140-30

Unit

7C141-30

Min Max

–

15

–

20

–

20 ns

–

15

–

20

–

20 ns

–

15

–

20

–

20 ns

–

15

–

20

–

20 ns

5

–

5

–

5

–

ns

0

–

0

–

0

–

ns

13

–

20

–

30

–

ns

–

15

–

25

–

30 ns

– Note 22 – Note 22 – Note 22 ns

– Note 22 – Note 22 – Note 22 ns

–

15

–

25

–

25 ns

–

15

–

25

–

25 ns

–

15

–

25

–

25 ns

–

15

–

25

–

25 ns

–

15

–

25

–

25 ns

–

15

–

25

–

25 ns

Notes

20. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.

21. CY7C140/CY7C141 only.

22. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:

BUSY on Port B goes HIGH.

Port B’s address is toggled.

CE for Port B is toggled.

R/W for Port B is toggled during valid read.

Document Number: 38-06002 Rev. *H

Page 8 of 22

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