CY7C130A 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C130A Datasheet PDF : 22 Pages
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Switching Characteristics
Over the Operating Range[12, 13]
Parameter
Description
Read Cycle
tRC
Read cycle time
tAA
Address to data valid[15]
tOHA
Data hold from address change
tACE
CE LOW to data valid[15]
tDOE
OE LOW to data valid[15]
tLZOE
OE LOW to low Z[16, 17, 18]
tHZOE
OE HIGH to high Z[16, 17, 18]
tLZCE
CE LOW to low Z[16, 17, 18]
tHZCE
CE HIGH to high Z[16, 17, 18]
tPU
CE LOW to power-up[16]
tPD
CE HIGH to power-down[16]
Write Cycle[19]
tWC
Write cycle time
tSCE
CE LOW to write end
tAW
Address setup to write end
tHA
Address hold from write end
tSA
Address setup to write start
tPWE
R/W pulse width
tSD
Data setup to write end
tHD
tHZWE
tLZWE
Data hold from write end
R/W LOW to high Z[18]
R/W HIGH to low Z[18]
Shaded areas contain preliminary information.
CY7C130, CY7C130A
CY7C131, CY7C131A
7C131-15[14]
7C131A-15
7C141-15
Min Max
7C130-25[14]
7C131-25
7C140-25
7C141-25
Min Max
7C130-30
7C130A-30
7C131-30
7C140-30
Unit
7C141-30
Min Max
15
–
25
–
30
–
ns
–
15
–
25
–
30 ns
0
–
0
–
0
–
ns
–
15
–
25
–
30 ns
–
10
–
15
–
20 ns
3
–
3
–
3
–
ns
–
10
–
15
–
15 ns
3
–
5
–
5
–
ns
–
10
–
15
–
15 ns
0
–
0
–
0
–
ns
–
15
–
25
–
25 ns
15
–
25
–
30
–
ns
12
–
20
–
25
–
ns
12
–
20
–
25
–
ns
2
–
2
–
2
–
ns
0
–
0
–
0
–
ns
12
–
15
–
25
–
ns
10
–
15
–
15
–
ns
0
–
0
–
0
–
ns
–
10
–
15
–
15 ns
0
–
0
–
0
–
ns
Notes
12. See the last page of this specification for Group A subgroup testing information.
13. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and output loading of the specified
IOL/IOH, and 30 pF load capacitance.
14. 15 and 25 ns version available only in PLCC/PQFP packages.
15. AC Test Conditions use VOH = 1.6 V and VOL = 1.4 V.
16. This parameter is guaranteed but not tested.
17. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
18. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
19. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document Number: 38-06002 Rev. *H
Page 7 of 22
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