CY7C038-20AC(1998) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C038-20AC Datasheet PDF : 18 Pages
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51
PRELIMINARY
CY7C027/028
CY7C037/038
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 32K x 16 organization (CY7C027)
• 64K x 16 organization (CY7C028)
• 32K x 18 organization (CY7C037)
• 64K x 18 organization (CY7C038)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12[1]/15/20 ns
• Low operating power
— Active: ICC = 180 mA (typical)
— Standby: ISB3 = 0.05 mA (typical)
Logic Block Diagram
R/WL
UBL
32K/64K x 16/18
Dual-Port Static RAM
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using Mas-
ter/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Separate upper-byte and lower-byte control
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to IDT7027
R/WR
UBR
CE0L
CE1L
LBL
OEL
CEL
[2]
8/9
I/O8/9L–I/O15/17L
[3]
8/9
I/O0L–I/O7/8L
I/O
Control
I/O
Control
CER
CE0R
CE1R
LBR
OER
8/9
[2]
I/O8/9L–I/O15/17R
8/9
[3]
I/O0L–I/O7/8R
[4]
A0L–A14/15L
15/16
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
15/16
[4]
A0R–A14/15R
[4]
A0L–A14/15L
15/16
15/16
[4]
A0R–A14/15R
CEL
OEL
R/WL
SEML
BUSYL[5]
INTL
UBL
LBL
Interrupt
Semaphore
Arbitration
M/S
CER
OER
R/WR
SEMR
[5]
BUSYR
INTR
UBR
LBR
Notes:
1. See page 6 for Load Conditions.
2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
3. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices.
4. A0–A14 for 32K; A0–A15 for 64K devices.
5. BUSY is an output in master mode and an input in slave mode.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 23, 1998
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