CY7B9911 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7B9911

Programmable Skew Clock Buffer

Cypress Semiconductor 

CY7B9911

RoboClock+™

Figure 3. Zero Skew and Zero Delay Clock Driver

SYSTEM

CLOCK

REF

FB

REF

FS

4F0

4Q0

4F1

4Q1

3F0

3Q0

3F1

3Q1

2F0

2Q0

2F1

2Q1

1F0

1Q0

1F1

1Q1

TEST

LENGTH L1 = L2 = L3 = L4

LOAD

L1

Z0

LOAD

L2

Z0

L3

Z0

LOAD

L4

LOAD

Z0

Operational Mode Descriptions

Figure 2 shows the PSCB configured as a zero skew clock buffer. In this mode the 7B9911 is used as the basis for a low skew clock

distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and each drive a terminated

transmission line to an independent load. The FB input is tied to any output in this configuration and the operating frequency range

is selected with the FS pin. The low skew specification, coupled with the ability to drive terminated transmission lines (with impedances

as low as 50 ohms), enables efficient printed circuit board design.

Figure 4. Programmable Skew Clock Driver

REF

LOAD

SYSTEM

CLOCK

FB

REF

FS

4F0

4Q0

4F1

4Q1

3F0

3Q0

3F1

3Q1

2F0

2Q0

2F1

2Q1

1F0

1Q0

1F1

1Q1

TEST

LENGTH L1 = L2

L3 < L2 by 6 inches

L4 > L2 by 6 inches

L1

Z0

LOAD

L2

Z0

L3

Z0

LOAD

L4

LOAD

Z0

Figure 3 shows a configuration to equalize skew between metal

traces of different lengths. In addition to low skew between

outputs, the PSCB is programmed to stagger the timing of its

outputs. The four groups of output pairs are each programmed

to different output timing. Skew timing is adjusted over a wide

range in small increments with the appropriate strapping of the

function select pins. In this configuration the 4Q0 output is sent

to FB and configured for zero skew. The other three pairs of

outputs are programmed to yield different skews relative to the

feedback. By advancing the clock signal on the longer traces or

retarding the clock signal on shorter traces, all loads receive the

clock pulse at the same time.

In this illustration the FB input is connected to an output with 0

ns skew (xF1, xF0 = MID) selected. The internal PLL synchro-

nizes the FB and REF inputs and aligns their rising edges to

make certain that all outputs have precise phase alignment.

Clock skews is advanced by ±6 time units (tU) when using an

output selected for zero skew as the feedback. There is a wider

Document Number: 38-07209 Rev. *C

Page 9 of 13

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