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CY7B9911

Programmable Skew Clock Buffer

Cypress Semiconductor 

CY7B9911

RoboClock+™

Figure 7 shows some of the functions that are selectable on the

3Qx and 4Qx outputs. These include inverted outputs and

outputs that offer divide-by-2 and divide-by-4 timing. An inverted

output allows the system designer to clock different subsystems

on opposite edges, without suffering from the pulse asymmetry

typical of non-ideal loading. This function enables each of the

two subsystems to clock 180 degrees out of phase, but still stay

aligned within the skew specification.

The divided outputs offer a zero delay divider for portions of the

system that divides the clock by either two or four, and still remain

within a narrow skew of the “1X” clock. Without this feature,

addition of an external divider is required and the propagation

delay of the divider adds to the skew between the different clock

signals.

These divided outputs, coupled with the Phase Locked Loop,

enable the PSCB to multiply the clock rate at the REF input by

either two or four. This mode enables the designer to distribute

a low frequency clock between various portions of the system. It

also locally multiplies the clock rate to a more suitable frequency,

maintaining the low skew characteristics of the clock driver. The

PSCB performs all of the functions described in this section at

the same time. It can multiply by two and four or divide by two

(and four) at the same time that it is shifting its outputs over a

wide range or maintaining zero skew between selected outputs.

Figure 8. Multi-Function Clock Driver

20 MHz

DISTRIBUTION

CLOCK

REF

FB

REF

FS

4F0

4Q0

4F1

4Q1

3F0

3Q0

3F1

3Q1

2F0

2Q0

2F1

2Q1

1F0

1Q0

1F1

1Q1

TEST

Z0

80 MHz

INVERTED

20 MHz

Z0

80 MHz

ZEROSKEW

Z0

LOAD

LOAD

LOAD

80 MHz

SKEWED4ns

LOAD

Z0

Figure 9. Board-to-Board Clock Distribution

SYSTEM

CLOCK

REF

FB

REF

FS

4F0

4Q0

4F1

4Q1

3F0

3Q0

3F1

3Q1

2F0

2Q0

2F1

2Q1

1F0

1Q0

1F1

1Q1

TEST

L1

L2

LOAD

Z0

LOAD

Z0

L3

L4

Z0

Z0

FB

REF

FS

4F0

4F1

4Q0

4Q1

3F0 3Q0

3F1 3Q1

2F0 2Q0

2F1 2Q1

1F0 1Q0

1F1 1Q1

TEST

LOAD

LOAD

LOAD

Document Number: 38-07209 Rev. *C

Page 11 of 13

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