CXD1159AQ 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD1159AQ

Sync Signal Generator for Camera

Sony Semiconductor 

CXD1159AQ

• Initialize (VINT)

When EXT = L, VINT fall is detected and operation is started as the circuit is initialized at the VD fall position

just before field I. (Initialization is completed within 100ns after the fall is detected).

NTSC VINT

VD

HD

FLD

Initialize point

PAL VINT

VD

HD

FLD

Initialize point

• H reset (HR)

Reset is performed with the first fall. However reset is not done anymore unless there is a deviation of more

than 2 clocks (0.98µs) to the subsequent edges.

The minimum reset pulse width is 0.98µs.

HD is reset 2.94 to 3.43µs in advance of HR input.

more than 0.98µs

HR

HD

2.94 to 3.43µs

• V reset (VR)

VD is reset 3.5H in advance of VR input.

The minimum reset pulse width is 32µs.

• LALT reset (LR)

LALT is reset in the same phase as LR reset.

The minimum reset pulse width is 32µs.

LR

LALT

–6–

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