CS61305A 데이터 시트보기 (PDF) - Cirrus Logic
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CS61305A Datasheet PDF : 44 Pages
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CS61305A
T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol Min
Typ
Max Units
Crystal Frequency
ACLKI Duty Cycle
ACLKI Frequency
RCLK Cycle Width
Rise Time, All Digital Outputs
Fall Time, All Digital Outputs
TCLK Frequency
TCLK Pulse Width
(Note 23)
(Note 24)
(Note 25)
(Note 26)
(Note 26)
(Notes 16, 27, 28)
(Notes 29, 30)
fc
tpwh3/tpw3
faclki
tpw1
tpwh1
tpwl1
tr
tf
ftclk
tpwh2
-
6.176000 -
MHz
40
-
60
%
-
1.544
-
MHz
320
648
980 ns
130
190
240 ns
100
458
850 ns
-
-
85
ns
-
-
85
ns
-
1.544
-
MHz
80
-
-
ns
150
-
500 ns
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2
25
-
-
ns
RPOS/RNEG Valid Before RCLK Falling
(Note 27) tsu1
150
274
-
ns
RDATA Valid Before RCLK Falling
(Note 29) tsu1
150
274
-
ns
RPOS/RNEG Valid Before RCLK Rising
(Note 28) tsu1
150
274
-
ns
RPOS/RNEG Valid After RCLK Falling
(Note 27)
th1
150
274
-
ns
RDATA Valid After RCLK Falling
(Note 29)
th1
150
274
-
ns
RPOS/RNEG Valid After RCLK Rising
(Note 28)
th1
150
274
-
ns
Notes: 23. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.
24. ACLKI provided by an external source or TCLK but not RCLK.
25. RCLK duty cycle will vary with extent by which pulses are displaced by jitter. Specified under worst
case jitter conditions: 0.4 UI AMI data displacement for T1 and 0.2 UI AMI data displacement for E1.
26. At max load of 1.6 mA and 50 pF.
27. Host Mode (CLKE = 1).
28. Hardware Mode, or Host Mode (CLKE = 0).
29. Extended Hardware Mode.
30. The maximum TCLK burst rate is 5 MHz and tpw2 (min) = 200ns. The maximum gap size that can
be tolerated on TCLK is 138 VI.
DS157PP3
5
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