PACKAGE PIN DESCRIPTION
PACKAGE PIN #
SO−16
SO−24L
1
1
2
2
3
−
−
3
4
4
−
5−8, 17−20
5
9
6
10
7
11
8
12
9
13
10
14
11
15
12
16
13
21
14
22
15
23
16
24
CS5422
PIN SYMBOL
GATE(H)1
GATE(L)1
GND
PGND
BST
LGND
IS+1
IS−1
VFB1
FUNCTION
High Side Switch FET driver pin for channel 1.
Low Side Synchronous FET driver pin for channel 1.
Ground pin for all circuitry contained in the IC. This pin is internally
bonded to the substrate of the IC.
Ground pin for the FET drivers.
Power input for GATE(H)1 and GATE(H)2 pins.
Ground pin for the internal control circuitry. The pin is internally
bonded to the substrate of the IC.
Positive input for channel 1 overcurrent comparator.
Negative input for channel 1 overcurrent comparator.
Error amplifier inverting input for channel 1.
COMP1
COMP2
VFB2
IS−2
IS+2
ROSC
VCC
GATE(L)2
GATE(H)2
Channel 1 Error Amp output. PWM Comparator reference input. A
capacitor to LGND provides Error Amp compensation. The same
capacitor provides Soft Start timing for channel 1. This pin also
disables the channel 1 output when pulled below 0.3 V.
Channel 2 Error Amp output. PWM Comparator reference input. A
capacitor to LGND provides Error Amp compensation and Soft
Start timing for channel 2. Channel 2 output is disabled when this
pin is pulled below 0.3 V.
Error amplifier inverting input for channel 2.
Negative input for channel 2 overcurrent comparator.
Positive input for channel 2 overcurrent comparator.
Oscillator frequency pin. A resistor from this pin to ground sets the
oscillator frequency.
Input Power supply pin.
Low Side Synchronous FET driver pin for channel 2.
High Side Switch FET driver pin for channel 2.
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