CS5422 데이터 시트보기 (PDF) - ON Semiconductor

부품명

상세내역

일치하는 목록

CS5422

Dual Out−of−Phase Synchronous Buck Controller with Current Limit

ON Semiconductor 

CS5422

Figure 6. Hiccup Overcurrent Protection

Output Enable

On/Off control of the regulator outputs can be implemented

by pulling the COMP pins low. The COMP pins must be

driven below the 0.45 V PWM comparator offset voltage in

order to disable the switching of the GATE drivers.

DESIGN GUIDELINES

Definition of the design specifications

The output voltage tolerance can be affected by any or all

of the following reasons:

1. buck regulator output voltage setpoint accuracy;

2. output voltage change due to discharging or charging

of the bulk decoupling capacitors during a load

current transient;

3. output voltage change due to the ESR and ESL of the

bulk and high frequency decoupling capacitors,

circuit traces, and vias;

4. output voltage ripple and noise.

Budgeting the tolerance is left up to the designer who must

take into account all of the above effects and provide an

output voltage that will meet the specified tolerance at the

load.

The designer must also ensure that the regulator component

temperatures are kept within the manufacturer’s specified

ratings at full load and maximum ambient temperature.

Selecting Feedback Divider Resistors

VOUT

R1

VFB

R2

The feedback pins (VFB1(2)) are connected to external

resistor dividers to set the output voltages. The error

amplifier is referenced to 1.0 V and the output voltage is

determined by selecting resistor divider values. Resistor R1

is selected based on a design trade−off between efficiency

and output voltage accuracy. The output voltage error can be

estimated due to the bias current of the error amplifier

neglecting resistor tolerance:

Error% + 1

10*6

1

R1 100%

R2 can be sized after R1 has been determined:

ǒ Ǔ R2 + R1

VREF

VO * VREF

Calculating Duty Cycle

The duty cycle of a buck converter (including parasitic

losses) is given by the formula:

Duty

Cycle

+

D

+

VOUT ) (VHFET ) VL)

VIN ) VLFET * VHFET *

VL

where:

VOUT = buck regulator output voltage;

VHFET = high side FET voltage drop due to RDS(ON);

VL = output inductor voltage drop due to inductor wire

DC resistance;

VIN = buck regulator input voltage;

VLFET = low side FET voltage drop due to RDS(ON).

Selecting the Switching Frequency

Selecting the switching frequency is a trade−off between

component size and power losses. Operation at higher

switching frequencies allows the use of smaller inductor and

capacitor values. Nevertheless, it is common to select lower

frequency operation because a higher frequency results in

lower efficiency due to MOSFET gate charge losses.

Additionally, the use of smaller inductors at higher

frequencies results in higher ripple current, higher output

voltage ripple, and lower efficiency at light load currents.

The value of the oscillator resistor is designed to be

linearly related to the switching period. If the designer

prefers not to use Figure 8 to select the necessary resistor, the

following equation quite accurately predicts the proper

resistance for room temperature conditions.

ROSC

+

21700 * fSW

2.31fSW

where:

ROSC = oscillator resistor in kΩ;

fSW = switching frequency in kHz.

Figure 7. Selecting Feedback Divider Resistors

http://onsemi.com

10

Share Link: