CDB4222(1997) 데이터 시트보기 (PDF) - Cirrus Logic

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CDB4222
(Rev.:1997)

20-Bit Stereo Audio Codec with Volume Control

Cirrus Logic 

CS4222

SWITCHING CHARACTERISTICS - CONTROL PORT

(TA = 25°C; VD, VA = 5V±5%; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30pF)

Parameter

Symbol Min

Max

I2C® Mode (SPI/I2C = 1)

(Note 12)

SCL Clock Frequency

fscl

-

100

RST Rising Edge to Start

tirs

500

-

Bus Free Time Between Transmissions

tbuf

4.7

-

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

-

Clock Low Time

tlow

4.7

-

Clock High Time

thigh

4.0

-

Setup Time for Repeated Start Condition

tsust

4.7

-

SDA Hold Time from SCL Falling

(Note 13)

thdd

0

-

SDA Setup Time to SCL Rising

tsud

250

-

Rise Time of Both SDA and SCL Lines

tr

-

1

Fall Time of Both SDA and SCL Lines

tf

-

300

Setup Time for Stop Condition

tsusp

4.7

Notes: 12. Use of the I2C® bus interface requires a license from Philips.

I2C® is a registered trademark of Philips Semiconductors.

13. Data must be held for sufficient time to bridge the 300ns transition time of SCL.

Units

kHz

ns

µs

µs

µs

µs

µs

µs

ns

µs

ns

µs

RST

t irs

Stop

Start

Repeated

Start

SDA

SCL

t buf

t hdst

t high

t hdst

tf

t low t hdd

t sud

t sust

tr

Stop

t susp

6

DS236PP3

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