CDB4222(1997) 데이터 시트보기 (PDF) - Cirrus Logic

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CDB4222
(Rev.:1997)

20-Bit Stereo Audio Codec with Volume Control

Cirrus Logic 

SWITCHING CHARACTERISTICS - CONTROL PORT

(TA = 25°C VD, VA = 5V±5%; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30pF)

Parameter

Symbol

Min

SPI Mode (SPI/I2C = 0)

CCLK Clock Frequency

fsck

-

RST rising edge to CS falling

tsrs

500

CCLK edge to CS falling

(Note 9)

tspi

500

CS High Time Between Transmissions

tcsh

1.0

CS Falling to CCLK Edge

tcss

20

CCLK Low Time

tscl

66

CCLK High Time

tsch

66

CDIN to CCLK Rising Setup Time

tdsu

40

CCLK Rising to DATA Hold Time

(Note 10)

tdh

15

Rise Time of CCLK and CDIN

(Note 11)

tr2

-

Fall Time of CCLK and CDIN

(Note 11)

tf2

-

Notes: 9. tspi only needed before first falling edge of CS after RST rising edge.

tspi = 0 at all other times.

10. Data must be held for sufficient time to bridge the transition time of CCLK.

11. For FSCK < 1 MHz

CS4222

Max Units

6

MHz

-

ns

-

ns

-

µs

-

ns

-

ns

-

ns

-

ns

-

ns

100

ns

100

ns

RST

t srs

CS

t spi t css

t scl t sch

t csh

CCLK

t r2

t f2

CDIN

t dsu t dh

DS236PP3

5

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