CM2030(2012) 데이터 시트보기 (PDF) - ON Semiconductor
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CM2030 Datasheet PDF : 11 Pages
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CM2030
BACKDRIVE PROTECTION AND ISOLATION
Backdrive current is defined as the undesirable current
flow through an I/O pin when that I/O pin’s voltage exceeds
the related local supply voltage for that circuitry. This is
a potentially common occurrence in multimedia
entertainment systems with multiple components and
several power plane domains in each system.
For example, if a DVD player is switched off and an
HDMI connected TV is powered on, there is a possibility of
reverse current flow back into the main power supply rail of
the DVD player from pull−ups in the TV. As little as a few
milliamps of backdrive current flowing back into the power
rail can charge the DVD player’s bulk bypass capacitance on
the power rail to some intermediate level. If this level rises
above the power−on−reset (POR) voltage level of some of
the integrated circuits in the DVD player, then these devices
may not reset properly when the DVD player is turned back
on.
If any SOC devices are incorporated in the design which
have built−in level shifter and/or ESD protection structures,
there can be a risk of permanent damage due to backdrive.
In this case, backdrive current can forward bias the on−chip
ESD protection structure. If the current flow is high enough,
even as little as a few milliamps, it could destroy one of the
SOC chip’s internal DRC diodes, as they are not designed for
passing DC.
To avoid either of these situations, the CM2030 was
designed to block backdrive current, guaranteeing less than
5 mA into any I/O pin when the I/O pin voltage exceeds its
related operating CM2030 supply voltage.
Figure 1. Backdrive Protection Diagram.
DISPLAY DATA CHANNEL (DDC) LINES
The DDC interface is based on the I2C serial bus protocol
for EDID configuration.
Dynamic Pullups
Based on the HDMI specification, the maximum
capacitance of the DDC line can approach 800 pF (50 pF
from source, 50 pF from sink, and 700 pF from cable). At
the upper range of capacitance values (i.e. long cables), it
becomes impossible for the DDC lines to meet the I2C
timing specifications with the minimum pull−up resistor of
1.5 kΩ.
For this reason, the CM2030 was designed with an
internal I2C accelerator to meet the AC timing specification
even with very long and non−compliant cables.
The internal accelerator increases the positive slew rate of
the DDC_CLK_OUT and DDC_DAT_OUT lines whenever
the sensed voltage level exceeds 0.3*5V_SUPPLY
(approximately 1.5 V). This provides faster overall risetime
in heavily loaded situations without overloading the
multi−drop open drain I2C outputs elsewhere.
Figure 2 demonstrates the “worst case” operation of the
dynamic CM2030 DDC level shifting circuitry (bottom)
against a discrete NFET common−gate level shifter circuit
with a typical 1.5 kW pullup at the source (top.) Both are
shown driving an off−spec, but unfortunately readily
available 31 m HDMI cable which exceeds the 700 pF
HDMI specification. Some widely available HDMI cables
have been measured at over 4 nF.
When the standard I/OD cell releases the NFET discrete
shifter, the risetime is limited by the pullup and the parasitics
of the cable, source and sink. For long cables, this can extend
the risetime and reduce the margin for reading a valid “high”
level on the data line. In this case, an HDMI source may not
be able to read uncorrupted data and will not be able to
initiate a link.
With the CM2030’s dynamic pullups, when the ASIC
driver releases its DDC line and the “OUT” line reaches at
least 0.3*VDD (of 5V_SUPPLY), then the “OUT” active
pullups are enabled and the CM2030 takes over driving the
cable until the “OUT” voltage approaches the 5V_SUPPLY
rail.
The internal pass element and the dynamic pullups also
work together to damp reflections on the longer cables and
keep them from glitching the local ASIC.
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